Canaan Inc. /K210 /DMAC /channel[0] /cfg

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Interpret as cfg

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (contiguous)src_multblk_type 0dst_multblk_type

src_multblk_type=contiguous, lock_ch_l=dma_transfer, src_hwhs_pol=active_high, hs_sel_src=hardware, tt_fc=mem2mem_dma

Description

Configure Register

Fields

src_multblk_type

Source multi-block transfer type

0 (contiguous): Continuous multi-block type

1 (reload): Reload multi-block type

2 (shadow_register): Shadow register based multi-block type

3 (linked_list): Linked list based multi-block type

dst_multblk_type

Destination multi-block transfer type

tt_fc

Transfer type and flow control

0 (mem2mem_dma): Transfer memory to memory and flow controller is DMAC

1 (mem2prf_dma): Transfer memory to peripheral and flow controller is DMAC

2 (prf2mem_dma): Transfer peripheral to memory and flow controller is DMAC

3 (prf2prf_dma): Transfer peripheral to peripheral and flow controller is DMAC

4 (prf2mem_prf): Transfer peripheral to memory and flow controller is source peripheral

5 (prf2prf_srcprf): Transfer peripheral to peripheral and flow controller is source peripheral

6 (mem2prf_prf): Transfer memory to peripheral and flow controller is destination peripheral

7 (prf2prf_dstprf): Transfer peripheral to peripheral and flow controller is destination peripheral

hs_sel_src

Source software or hardware handshaking select

0 (hardware): Hardware handshaking is used

1 (software): Software handshaking is used

hs_sel_dst

Destination software or hardware handshaking select

src_hwhs_pol

Source hardware handshaking interface polarity

0 (active_high): Active high

1 (active_low): Active low

dst_hwhs_pol

Destination hardware handshaking interface polarity

src_per

Assign a hardware handshaking interface to source of channel

dst_per

Assign a hardware handshaking interface to destination of channel

ch_prior

Channel priority (7 is highest, 0 is lowest)

lock_ch

Channel lock bit

lock_ch_l

Channel lock level

0 (dma_transfer): Duration of channel is locked for entire DMA transfer

1 (block_transfer): Duration of channel is locked for current block transfer

2 (transaction): Duration of channel is locked for current transaction

src_osr_lmt

Source outstanding request limit

dst_osr_lmt

Destination outstanding request limit

Links

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